The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. Such advances have increased the complexity and challenges of processing and manufacturing of ICs.
Vertically-conducting trench MOSFETs (metal oxide semiconductor field effect transistors) can be used as power electronics. When a trench MOSFET is biased in the on state, current flows vertically between source regions and substrate. Reducing cell pitch of MOSFETs is crucial in reducing the device sizes and in increasing the number of active devices on a semiconductor chip. In addition, cell pitch also affect device performance, such as the resistivity between source and drain when the device is on (Rdson). Reducing cell pitch is limited by the manufacturing process technology, such the capability of lithographical tool in resolving minimum critical dimension and in aligning different patterning layers. It is within this context the following disclosure arises.